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1 LTC1746 1746f applicatio s u features descriptio u block diagra w low power,14-bit, 25msps adc n sample rate: 25msps n 77.5db snr and 91db sfdr (3.2v range) n 74db snr and 96db sfdr (2v range) n no missing codes n single 5v supply n low power dissipation: 390mw n selectable input ranges: 1v or 1.6v n 240mhz full power bandwidth s/h n pin compatible family 25 msps: LTC1746 (14-bit), ltc1745 (12-bit) 50 msps: ltc1744 (14-bit), ltc1743 (12-bit) 65 msps: ltc1742 (14-bit), ltc1741 (12-bit) 80 msps: ltc1748 (14-bit), ltc1747 (12-bit) n telecommunications n medical imaging n receivers n base stations n spectrum analysis n imaging systems , ltc and lt are registered trademarks of linear technology corporation. the ltc ? 1746 is a 25msps, sampling 14-bit a/d con- verter designed for digitizing high frequency, wide dy- namic range signals. pin selectable input ranges of 1v and 1.6v along with a resistor programmable mode allow the LTC1746s input range to be optimized for a wide variety of applications. the LTC1746 is perfect for demanding communications applications with ac performance that includes 77.5db snr and 91db spurious free dynamic range. ultralow jitter of 0.3ps rms allows undersampling with excellent noise performance. dc specs include 3lsb inl maximum and no missing codes over temperature. the digital interface is compatible with 5v, 3v and 2v logic systems. the enc and enc inputs may be driven differen- tially from pecl, gtl and other low swing logic families or from single-ended ttl or cmos. the low noise, high gain enc and enc inputs may also be driven by a sinusoidal signal without degrading performance. a separate digital output power supply can be operated from 0.5v to 5v, making it easy to connect directly to low voltage dsps or fifos. the tssop package with a flow-through pinout simplifies the board layout. 25msps, 14-bit adc with a 1v differential input range 14-bit pipelined adc 14 s/h amp 1v differential analog input a in + a in sense v cm 4.7 f diff amp refla refhb gnd 1746 bd enc 4.7 f 1 f1 f 0.1 f 0.1 f refha reflb buffer range select 2.35v ref output latches control logic ov dd v dd ognd 0.5v to 5v 5v 0.1 f 1 f 1 f 1 f d13 d0 clkout of enc differential encode input oe msbinv 0.1 f
2 LTC1746 1746f parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error (note 6) l C3 1 3 lsb differential linearity error l C1 0.5 1 lsb offset error (note 7) l C30 530 mv gain error external reference (sense = 1.6v) l C 2.5 1 2.5 %fs full-scale tempco i out(ref) = 0 40 ppm/ c order part number ov dd = v dd (notes 1, 2) supply voltage (v dd ) ............................................. 5.5v analog input voltage (note 3) .... C 0.3v to (v dd + 0.3v) digital input voltage (note 4) ..... C 0.3v to (v dd + 0.3v) digital output voltage ................. C 0.3v to (v dd + 0.3v) ognd voltage .............................................. C 0.3v to 1v power dissipation ............................................ 2000mw operating temperature range LTC1746c ............................................... 0 c to 70 c LTC1746i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c LTC1746cfw LTC1746ifw t jmax = 150 c, q ja = 35 c/w the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) absolute m axi m u m ratings w ww u package/order i n for m atio n w uu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view fw package 48-lead plastic tssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 sense v cm gnd a in + a in gnd v dd v dd gnd reflb refha gnd gnd refla refhb gnd v dd v dd gnd v dd gnd msbinv enc enc of ognd d13 d12 d11 ov dd d10 d9 d8 d7 ognd gnd gnd d6 d5 d4 ov dd d3 d2 d1 d0 ognd clkout oe co verter characteristics u symbol parameter conditions min typ max units v in analog input range (note 8) 4.75v v dd 5.25v l 1 to 1.6 v i in analog input leakage current l C1 1 m a c in analog input capacitance sample mode enc < enc 8 pf hold mode enc > enc 4 pf t acq sample-and-hold acquisition time l 15 18 ns t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.3 ps rms cmrr analog input common mode rejection ratio 1.0v < (a in C = a in + ) < 3.5v 80 db the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) a alog i put u u consult ltc marketing for parts specified with wider operating temperature ranges.
3 LTC1746 1746f symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input signal (2v range) 74 dbfs 5mhz input signal (3.2v range) l 75.5 77.5 dbfs 30mhz input signal (2v range) 73.5 dbfs 30mhz input signal (3.2v range) 76.5 dbfs 70mhz input signal (2v range) 72.5 dbfs 70mhz input signal (3.2v range) 75 dbfs sfdr spurious free dynamic range 5mhz input signal (2v range) 96 db 5mhz input signal (3.2v range) l 80 91 db 30mhz input signal (2v range) 95 db 30mhz input signal (3.2v range) 86.5 db 70mhz input signal (2v range) 79 db 70mhz input signal (3.2v range) 71 db s/(n + d) signal-to-(noise + distortion) ratio 5mhz input signal (2v range) 74 dbfs 5mhz input signal (3.2v range) l 75 77.5 dbfs 30mhz input signal (2v range) 73.5 dbfs 30mhz input signal (3.2v range) 76.5 dbfs 70mhz input signal (2v range) 71.5 dbfs 70mhz input signal (3.2v range) 70 dbfs thd total harmonic distortion 5mhz input signal, first 5 harmonics (2v range) C 92 db 5mhz input signal, first 5 harmonics (3.2v range) C 90 db 30mhz input signal, first 5 harmonics (2v range) C 90.5 db 30mhz input signal, first 5 harmonics (3.2v range) C 85.5 db 70mhz input signal, first 5 harmonics (2v range) C77.5 db 70mhz input signal, first 5 harmonics (3.2v range) C70 db imd intermodulation distortion f in1 = 4mhz, f in2 = 5.1mhz (2v range) 86 dbc f in1 = 4mhz, f in2 = 5.1mhz (3.2v range) 84 dbc sample-and-hold bandwidth r source = 50 w 240 mhz the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = C1dbfs. (note 5) dy a ic accuracy u w parameter conditions min typ max units v cm output voltage i out = 0 2.29 2.35 2.41 v v cm output tempco i out = 0 30 ppm/ c v cm line regulation 4.75v v dd 5.25v 3 mv/v v cm output resistance 1ma ? i out ? 1ma 4 w (note 5) i ter al refere ce characteristics uu u
4 LTC1746 1746f symbol parameter conditions min typ max units f sample sampling frequency (note 9) l 1 25 mhz t 1 enc low time (note 9) l 19 20 1000 ns t 2 enc high time (note 9) l 19 20 1000 ns t 3 aperture delay of sample-and-hold (note 8) 0 ns t 4 enc to data delay c l = 10pf (note 8) l 1.4 4 10 ns t 5 enc to clkout delay c l = 10pf (note 8) l 0.5 2 5 ns t 6 clkout to data delay c l = 10pf (note 8) l 02 ns t 7 data access time after oe c l = 10pf (note 8) 10 25 ns t 8 bus relinquish time (note 8) 10 25 ns data latency 5 cycles symbol parameter conditions min typ max units v dd positive supply voltage 4.75 5.25 v i dd positive supply current 2v range, full-scale input l 78 93 ma p dis power dissipation 2v range, full-scale input l 390 465 mw ov dd digital output supply voltage 0.5 v dd v the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ti i g characteristics u w note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with gnd (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd, they will be clamped by internal diodes. this product can handle input currents of >100ma below gnd without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 25mhz, differential enc/enc = 2v p-p 25mhz sine wave, input range = 1.6v differential, unless otherwise specified. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar offset is the offset voltage measured from C 0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. note 8: guaranteed by design, not subject to test. note 9: recommended operating conditions. symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance msbinv and oe only 1.5 pf v oh high level output voltage ov dd = 4.75v i o = C10 m a 4.74 v i o = C 200 m a l 4v v ol low level output voltage ov dd = 4.75v i o = 160 m a 0.05 v i o = 1.6ma l 0.1 0.4 v i oz hi-z output leakage d13 to d0 v out = 0v to v dd , oe = high l 10 m a c oz hi-z output capacitance d13 to d0 oe = high (note 8) l 15 pf i source output source current v out = 0v C 50 ma i sink output sink current v out = 5v 50 ma the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) digital i puts a d digital outputs u u the l indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) power require e ts w u
5 LTC1746 1746f typical perfor a ce characteristics uw nonaveraged, 32768 point fft, input frequency = 5mhz, 3.2v range code 0 ?.0 inl error (lsb) 0.5 0 0.5 1.0 4000 8000 1746 g01 12000 16000 code 0 ?.0 dnl error (lsb) 0.5 0 0.5 1.0 4000 8000 1746 g02 12000 16000 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 0 ?0 2 6 812 ?0 ?0 4 10 1746 g03 typical inl typical dnl nonaveraged, 32768 point fft, input frequency = 30mhz, 2v range nonaveraged, 32768 point fft, input frequency = 30mhz, 3.2v range nonaveraged, 32768 point fft, input frequency = 5mhz, 2v range frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 0 ?0 2 6 812 ?0 ?0 4 10 1746 g04 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 0 ?0 2 6 812 ?0 ?0 4 10 1746 g05 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 0 ?0 2 6 812 ?0 ?0 4 10 1746 g06 nonaveraged, 32768 point 2-tone fft, input frequency = 4mhz and 5.1mhz, 3.2v range nonaveraged, 32768 point fft, input frequency = 70mhz, 2v range nonaveraged, 32768 point 2-tone fft, input frequency = 4mhz and 5.1mhz, 2v range frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 0 ?0 2 6 812 ?0 ?0 4 10 1746 g07 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 0 ?0 2 6 812 ?0 ?0 4 10 1746 g08 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?0 ?0 0 ?0 2 6 812 ?0 ?0 4 10 1746 g09
6 LTC1746 1746f typical perfor a ce characteristics uw grounded input histogram snr vs sample rate, input frequency = 5mhz, C1db code 8167 0 count 5000 10000 15000 20000 25000 8168 8169 8170 8171 1746 g10 8172 sample rate (msps) 0 66 snr (dbfs) 68 70 72 74 78 10 20 30 40 1746 g11 50 60 76 67 69 71 73 77 75 3.2v range 2v range sample rate (msps) 0 50 sfdr (db) 60 70 80 90 110 10 20 30 40 1746 g12 50 60 100 3.2v range 2v range sfdr vs sample rate, input frequency = 5mhz, C1db snr vs input frequency and amplitude 3.2v range snr vs input frequency and amplitude 2v range input frequency (mhz) 50 snr (db) 60 70 80 55 65 75 20 40 60 80 1746 g13 100 10 030507090 ?dbfs 6dbfs 20dbfs input frequency (mhz) 50 snr (db) 60 70 80 55 65 75 20 40 60 80 1746 g14 100 10 030507090 ?dbfs 6dbfs 20dbfs sfdr vs input frequency and amplitude, 3.2v range input frequency (mhz) 0 40 sfdr (dbfs) 50 70 80 90 110 10 50 70 1746 g15 60 100 40 90 100 20 30 60 80 ?dbfs 6dbfs 20dbfs sfdr vs input frequency and amplitude, 2v range input frequency (mhz) 0 40 sfdr (dbfs) 50 70 80 90 110 50 1746 g16 60 100 150 200 100 ?dbfs 6dbfs 20dbfs
7 LTC1746 1746f 2nd and 3rd harmonic vs input frequency, 3.2v range, C1db input frequency (mhz) 0 distortion (db) ?0 ?0 ?0 80 1746 g17 ?0 ?10 ?30 10 20 30 40 50 60 70 90 100 2nd harmonic 3rd harmonic typical perfor a ce characteristics uw input frequency (mhz) 0 distortion (db) ?0 ?0 ?0 100 1746 g18 ?0 ?10 ?30 50 150 200 2nd harmonic 3nd harmonic input frequency (mhz) 0 distortion (db) ?0 ?0 ?0 80 1746 g19 ?0 ?00 ?10 10 20 30 40 50 60 70 90 100 2nd and 3rd harmonic vs input frequency, 2v range, C1db worst harmonic 4th or higher vs input frequency, 3.2v range, C1db worst harmonic 4th or higher vs input frequency, 2v range, C1db input frequency (mhz) 0 distortion (db) ?0 ?0 ?0 100 1746 g20 ?0 ?00 ?10 50 150 200 sfdr vs input amplitude, 2v range, 5mhz input frequency input amplitude (dbfs) ?0 sfdr (dbc and dbfs) 80 90 sfdr dbfs sfdr dbc 1746 g21 70 60 ?0 ?0 0 110 100 power vs sample rate, input frequency = 5mhz sample rate (msps) 0 300 power (mw) 340 380 420 10 20 30 40 1746 g22 50 460 500 320 360 400 440 480 60 3.2v range 2v range
8 LTC1746 1746f sense (pin 1): reference sense pin. ground selects 1v. v dd selects 1.6v. greater than 1v and less than 1.6v applied to the sense pin selects an input range of v sense , 1.6v is the largest valid input range. v cm (pin 2): 2.35v output and input common mode bias. bypass to ground with 4.7 m f ceramic chip capacitor. gnd (pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): adc power ground. a in + (pin 4): positive differential analog input. a in C (pin 5): negative differential analog input. v dd (pins 7, 8, 17, 18, 20): 5v supply. bypass to gnd with 1 m f ceramic chip capacitor. reflb (pin 10): adc low reference. bypass to pin 11 with 0.1 m f ceramic chip capacitor. do not connect to pin 14. refha (pin 11): adc high reference. bypass to pin 10 with 0.1 m f ceramic chip capacitor, to pin 14 with a 4.7 m f ceramic capacitor and to ground with 1 m f ceramic capacitor. refla (pin 14): adc low reference. bypass to pin 15 with 0.1 m f ceramic chip capacitor, to pin 11 with a 4.7 m f ceramic capacitor and to ground with 1 m f ceramic capacitor. refhb (pin 15): adc high reference. bypass to pin 14 with 0.1 m f ceramic chip capacitor. do not connect to pin 11. pi fu ctio s uuu msbinv (pin 22): msb inversion control. low inverts the msb, 2s complement output format. high does not invert the msb, offset binary output format. enc (pin 23): encode input. the input sample starts on the positive edge. enc (pin 24): encode complement input. conversion starts on the negative edge. bypass to ground with 0.1 m f ceramic for single-ended encode signal. oe (pin 25): output enable. low enables outputs. logic high makes outputs hi-z. clkout (pin 26): data valid output. latch data on the rising edge of clkout. ognd (pins 27, 38, 47): output driver ground. d0-d3 (pins 28 to 31): digital outputs. d0 is the lsb. ov dd (pins 32, 43): positive supply for the output driv- ers. bypass to ground with 0.1 m f ceramic chip capacitor. d4-d6 (pins 33 to 35): digital outputs. d7-d10 (pins 39 to 42): digital outputs. d11-d13 (pins 44 to 46): digital outputs. d13 is the msb. of (pin 48): over/under flow output. high when an over or under flow has occurred.
9 LTC1746 1746f 14-bit pipelined adc 14 s/h amp 1v differential analog input a in + a in sense v cm 4.7 f diff amp refla refhb gnd 1746 bd enc 4.7 f 1 f1 f 0.1 f 0.1 f refha reflb buffer range select 2.35v ref output latches control logic ov dd v dd ognd 0.5v to 5v 5v 0.1 f 1 f 1 f 1 f d13 d0 clkout of enc differential encode input oe msbinv 0.1 f t 4 1746 td t 3 t 6 t 5 t 5 n t 1 t 2 data (n ?5) d11 to d0 analog input encode data clkout data (n ?4) d11 to d0 data (n ?3) d11 to d0 t 7 t 8 data n d11 to d0, of and clkout oe data ti i g diagra u ww fu ctio al block diagra uu w
10 LTC1746 1746f applicatio s i for atio wu uu dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s / (n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv vn v = +++ 20 234 1 222 2 ... where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodulation distortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc equals the enc voltage to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C 20log (2 p ) ? f in ? t jitter
11 LTC1746 1746f converter operation as shown in figure 1, the LTC1746 is a cmos pipelined multistep converter. the converter has four pipelined adc stages; a sampled analog input will result in a digitized value five cycles later, see the timing diagram section. the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. the en- code input is also differential for improved common mode noise immunity. the LTC1746 has two phases of operation, determined by the state of the differential enc/enc input pins. for brevity, the text will refer to enc greater than enc as enc high and enc less than enc as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. applicatio s i for atio wu uu diff ref amp ref buf internal clock signals internal references to adc differential input low jitter clock driver range select 2.35v reference enc enc output drivers shift register and correction oe msbinv ognd of ov dd 0.5v to 5v d13 d0 clkout 1746 f01 input s/h first stage sense v cm a in a in + 4.7 f second stage third stage fourth stage 5-bit pipelined adc stage 4-bit pipelined adc stage 4-bit pipelined adc stage 4-bit flash adc control logic refla refhb 4.7 f 1 f1 f 0.1 f 0.1 f refha reflb figure 1. functional block diagram
12 LTC1746 1746f when enc is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the sampled input is held. while enc is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of enc. when enc goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is re- peated for the third stage, resulting in a third stage residue that is sent to the fourth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample hold operation figure 2 shows an equivalent circuit for the LTC1746 cmos differential sample-and-hold. the differential ana- log inputs are sampled directly onto sampling capacitors (c sample ) through cmos transmission gates. this direct capacitor sampling results in the lowest possible noise for a given sampling capacitor size. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc/enc is low, the transmission gate connects the analog inputs to the sam- pling capacitors, and they charge to and track the differen- tial input voltage. when enc/enc transitions from low to high the sampled input voltage is held on the sampling capacitors. during the hold phase when enc/enc is high the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc/enc transitions from high to low the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve specified performance. each input should swing 0.8v for the 3.2v range or 0.5v for the 2v range, around a common mode voltage of 2.35v. the v cm output pin (pin 2) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a trans- former to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 4.7 m f or greater capacitor. applicatio s i for atio wu uu figure 2. equivalent input circuit c sample 4pf c parasitic 4pf c parasitic 4pf v dd LTC1746 a in + 1746 f02 c sample 4pf bias v dd 5v a in enc enc 2v 6k 2v 6k
13 LTC1746 1746f applicatio s i for atio wu uu input drive impedance as with all high performance, high speed adcs the dy- namic performance of the LTC1746 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can influence sfdr. at the falling edge of encode the sample- and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when encode rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capaci- tor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recomended to have a source impedence of 100 w or less for each input. the s/h circuit is optimized for a 50 w source impedance. if the source impedance is less than 50 w , a series resistor should be added to increase this impedance to 50 w . the source impedence should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the LTC1746 being driven by an rf transformer with a center tapped secondary. the second- ary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedence seen by the adc does not exceed 100 w for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequen- cies below 1mhz. figure 4 demonstrates the use of operational amplifiers to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain band- width of most op amps will limit the sfdr at high input frequencies. the 25 w resistors and 12pf capacitors on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequencies higher than 50mhz, the capacitors may need to be decreased to prevent excessive signal loss. figure 3. single-ended to differential conversion using a transformer figure 4. differential drive with op amps 1:1 25 0.1 f analog input v cm a in + a in 100 100 12pf 12pf 12pf 1746 f03 4.7 f 25 25 25 LTC1746 25 5v single-ended input 2.35v 1/2 range v cm a in + a in 12pf 12pf 12pf 1746 f04 4.7 f 25 25 100 500 500 25 LTC1746 + 1/2 lt1810 + 1/2 lt1810
14 LTC1746 1746f applicatio s i for atio wu uu reference operation figure 5 shows the LTC1746 reference circuitry consisting of a 2.35v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage refer- ence can be configured for two pin selectable input ranges of 2v( 1v differential) or 3.2v( 1.6v differential). tying the sense pin to ground selects the 2v range; tying the sense pin to v dd selects the 3.2v range. the 2.35v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor of 4.7 m f or larger is required for the 2.35v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference. it will not be stable without this capacitor. the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins: refha and refhb for the high reference and refla and reflb for the low reference. the doubled output pins are needed to reduce package inductance. bypass capacitors must be con- nected as shown in figure 5. other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in figure 6a. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device since the logic threshold is close to ground and v dd . the sense pin should be tied high or low as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 m f ceramic capacitor. v cm refha reflb sense tie to v dd for 3.2v range; tie to gnd for 2v range; range = 2 ?v sense for 1v < v sense < 1.6v 2.35v refla refhb 4.7 f 4.7 f internal adc high reference buffer 0.1 f 1746 f05 LTC1746 4 diff amp 1 f 1 f 0.1 f internal adc low reference 2.35v bandgap reference 1.6v 1v range detect and control figure 5. equivalent reference circuit v cm sense 2.35v 1.1v 4.7 f 12.5k 1 f 11k 1746 f06a LTC1746 v cm sense 2.35v 5v 1.25v 6 4 1, 2 4.7 f 1 f 0.1 f 1746 f06b LTC1746 lt1790-1.25 figure 6a. 2.2v range adc figure 6b. 2.5v range adc with an external reference
15 LTC1746 1746f applicatio s i for atio wu uu input range the input range can be set based on the application. for oversampled signal processing in which the input fre- quency is low (<10mhz), the largest input range will provide the best signal-to-noise performance while main- taining excellent sfdr. for high input frequencies (>10mhz), the 2v range will have the best sfdr perfor- mance but the snr will degrade by 3.5db. see the typical performance characteristics section. driving the encode inputs the noise performance of the LTC1746 can depend on the encode signal quality as much as on the analog input. the enc/enc inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 2v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. v dd LTC1746 1746 f07 bias v dd 5v enc enc analog input 2v bias 2v bias 1:4 0.1 f clock input 50 6k 6k to internal adc circuits figure 7. transformer driven enc/enc with equivalent encode input circuit 1746 f08a enc 2v v threshold = 2v enc 0.1 f LTC1746 1746 f08b enc enc 130 3.3v 3.3v 130 d0 q0 q0 mc100lvelt22 LTC1746 83 83 figure 8a. single-ended enc drive, not recommended for low jitter figure 8b. enc drive using a cmos-to-pecl translator
16 LTC1746 1746f applicatio s i for atio wu uu any noise present on the encode signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies) take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.8v to v dd . each input may be driven from ground to v dd for single-ended drive. maximum and minimum encode rates the maximum encode rate for the LTC1746 is 25msps. for the adc to operate properly the encode signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 19ns for the adc internal circuitry to have enough settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. at sample rates slower than 25msps the duty cycle can vary from 50% as long as each half cycle is at least 19ns. the lower limit of the LTC1746 sample rate is determined by the droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will dis- charge the capacitors. the specified minimum operating frequency for the LTC1746 is 1msps. digital outputs digital output buffers figure 9 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 w to external circuitry and may eliminate the need for external damping resistors. LTC1746 1746 f09 ov dd v dd v dd 0.1 f 43 typical data output ognd ov dd 0.5v to v dd predriver logic data from latch oe figure 9. equivalent circuit for a digital output buffer
17 LTC1746 1746f output loading as with all high speed/high resolution converters the digital output loading can affect the performance. the digital outputs of the LTC1746 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the output may be used but is not required since the adc has a series resistor of 43 w on chip. lower ov dd voltages will also help reduce interference from the digital outputs. format the LTC1746 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the msbinv pin; high selects offset binary. overflow bit an overflow output bit indicates when the converter is overranged or underranged. when of outputs a logic high the converter is either overranged or underranged. output clock the adc has a delayed version of the enc input available as a digital output, clkout. the clkout pin can be used to synchronize the converter data to the digital system. this is necessary when using a sinusoidal encode. data will be updated just after clkout falls and can be latched on the rising edge of clkout. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example if the converter is driving a dsp powered by a 3v supply then ov dd should be tied to that same 3v supply. ov dd can be powered with any voltage up to 5v. the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of and clkout. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. grounding and bypassing the LTC1746 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an inter- nal ground plane is recommended. the pinout of the LTC1746 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. applicatio s i for atio wu uu
18 LTC1746 1746f applicatio s i for atio wu uu high quality ceramic bypass capacitors should be used at the v dd, v cm , refha, refhb, refla and reflb pins as shown in the block diagram on the front page of this data sheet. bypass capacitors must be located as close to the pins as possible. of particular importance are the capaci- tors between refha and reflb and between refhb and refla. these capacitors should be as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recomended. the large 4.7 m f capacitor between refha and refla can be somewhat further away. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the LTC1746 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. an analog ground plane separate from the digital process- ing system ground should be used. all adc ground pins labeled gnd should connect to this plane. all adc v dd bypass capacitors, reference bypass capacitors and input filter capacitors should connect to this analog plane. the LTC1746 has three output driver ground pins, labeled ognd (pins 27, 38 and 47). these grounds should con- nect to the digital processing system ground. the output driver supply, ov dd should be connected to the digital processing system supply. ov dd bypass capacitors should bypass to the digital system ground. the digital process- ing system ground should be connected to the analog plane at adc ognd (pin 38). heat transfer most of the heat generated by the LTC1746 is transferred from the die through the package leads onto the printed circuit board. in particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. these pins have the lowest thermal resistance between the die and the outside envi- ronment. it is critical that all ground pins are connected to a ground plane of sufficient area. the layout of the evalu- ation circuit shown on the following pages has a low ther- mal resistance path to the internal ground plane by using multiple vias near the ground pins. a ground plane of this size results in a thermal resistance from the die to ambient of 35 c/w. smaller area ground planes or poorly connected ground pins will result in higher thermal resistance.
19 LTC1746 1746f fw package 48-lead plastic tssop (6.1mm) (reference ltc dwg # 05-08-1651) package descriptio u fw48 tssop 0502 0.09 ?0.20 (.0035 ?.008) 0 ?8 0.45 ?0.75 (.018 ?.029) 0.17 ?0.27 (.0067 ?.0106) 0.50 (.0197) bsc 6.0 ?6.2** (.236 ?.244) 7.9 ?8.3 (.311 ?.327) 134 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 12.4 ?12.6* (.488 ?.496) 1.20 (.0473) max 0.05 ?0.15 (.002 ?.006) 2 48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 47 c .10 -t- -c- millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale * ** 0.32 0.05 0.50 typ 6.2 0.10 8.1 0.10 recommended solder pad layout 0.95 0.10 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 LTC1746 1746f ? linear technology corporation 2003 lt/tp 0903 1k ? printed in the usa part number description comments lt1019 precision bandgap reference 0.05% max initial accuracy, 5ppm/ c max drift ltc1196 8-bit, 1msps serial adc 3v to 5v, so-8 ltc1405 12-bit, 5msps, sampling adc 5v or 5v pin compatible with the ltc1420 ltc1406 8-bit, 20msps adc undersampling capability up to 70mhz input ltc1410 12-bit, 1.25msps adc 5v, 71db sinad ltc1411 14-bit, 2.5msps adc 5v, no pipeline delay, 80db sinad ltc1412 12-bit, 3msps, sampling adc 5v, no pipeline delay, 72db sinad ltc1414 14-bit, 2.2msps adc 5v, 81db sinad and 95db sfdr ltc1415 single 5v, 12-bit, 1.25msps 55mw power dissipation, 72db sinad ltc1419 14-bit, 800ksps adc 5v, 95db sfdr ltc1420 12-bit, 10msps adc 71db sinad and 83db sfdr at nyquist lt1460 micropower precision series reference 0.075% accuracy, 10ppm/ c drift ltc1604/ltc1608 16-bit, 333ksps/500ksps adcs 16-bit, no missing codes, 90db sinad, C100db thd ltc1668 16-bit, 50msps dac 87db sfdr at 1mhz f out , low power, low cost ltc1740 14-bit, 6msps adc low power, 79db sinad, 91db sfdr ltc1741 12-bit, 65msps adc pin compatible with the LTC1746 ltc1742 14-bit, 65msps adc pin compatible with the LTC1746 ltc1743 12-bit, 50msps adc pin compatible with the LTC1746 ltc1744 14-bit, 50msps adc pin compatible with the LTC1746 ltc1745 12-bit, 25msps adc pin compatible with the LTC1746 ltc1747 12-bit, 80msps adc pin compatible with the LTC1746 ltc1748 14-bit, 80msps adc pin compatible with the LTC1746 related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com

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